Numbers are often represented in computers using a floating-point format. Two-input adders are often used to perform addition and subtraction (using the complement of one of the numbers) operations on floating-point numbers. To perform such operations on more than two floating-point numbers, multiple adders can be used to add up to two floating-point numbers at a time or multiple addition operations can be performed by a single adder. For example, to add three floating-point numbers, an adder can add two of the floating-point numbers and then add the third floating-point number to the sum of the first two numbers.
Floating-point addition can involve multiple steps including shifting bits to align the numbers based on their exponents, performing the addition, normalizing the sum, and rounding the sum if appropriate. Thus, performing more than one addition operation to add more than two floating-point numbers can result in multiple iterations of these steps. If multiple adders are used to compute the sums in parallel, the additional adders can take up more of the limited space of a chip that includes the adders.